S1D13505F00A Datasheet | Epson Electronics

DESCRIPTION The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile munications, Hand-Held PCs, and Office Automation. The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of differentiating features . Products requiring a “Portrait” mode display can take advantage of the Swivel View TM feature . Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features , bined with the S1D13505's Operating System independence, make it an ideal display solution for a wide variety of applications. s FEATURES x Memory Interface - 16-bit DRAM interface: - EDO-DRAM up to 40MHz data rate (80M bytes per second). - FPM-DRAM up to 25MHz data rate (50M bytes per second). - Memory size options: - 512K bytes using one 256K x 16 device. - 2M bytes using one 1M x 16 device. - Performance Enhancement Register to tailor the memory control output timing for the DRAM device. x CPU Interface - Supports the following interfaces: - 8/16-bit SH-4 bus interface. - 8/16-bit SH-3 bus interface. - 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers. - 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers. - Philips PR31500/PR31700 (MIPS). - Toshiba TX3912 (MIPS). - Philips PR31500/PR31700. - 16-bit Power PC (MPC821) microprocessor. - 16-bit Epson E0C33 microprocessor. - PC Card (PCMCIA). - Strong ARM (PC Card). - NEC VR41xx (MIPS). - ISA bus. - Supports the following interface with external logic: - GX486 microprocessor. - One-stage write buffer for minimum wait-state CPU writes. - Registers are memory-mapped - the M/R# pin selects between the display buffer and register...